1. Field of the Invention
The present invention relates to an over-erasure preventing device and method for controlling over-erasure of data stored in memory cells of a flash memory.
2. Description of Related Art
FIG. 8 is a cross-sectional view of a memory cell of a flash memory to which a conventional over-erasure preventing device is applied which is disclosed in Japanese patent application laid-open No. 9-35487/1997. In FIG. 8, the reference numeral 1 designates a control gate that is grounded when erasing data written in the memory cell; 2 designates a floating gate that contains electrons in a data written state; 3 designates an N-type source to which an erasing voltage of 12 V is applied for pulling out the electrons from the floating gate 2 when erasing data written in the memory cell; 4 designates an N-type drain that is placed at an open state when erasing the data written in the memory cell; and 5 designates a P-substrate.
Next, the operation of the conventional memory cell will be described.
First, the memory cell holds electrons in its floating gate 2 in the data written state, and the data can be erased by drawing out the electrons from the floating gate 2 to the N-type source 3.
The draw of the electrons from the floating gate 2 to the N-type source 3 for erasing data can be achieved by grounding the control gate 1 and applying the erasing voltage of 12 V to the N-type source 3 to cause the tunnel effect. However, repetitive application of the erasing voltage of the 12 V to the N-type source 3 for a long time will bring about a phenomenon that the floating gate 2 is positively charged, which will be referred to as "over-erasure" from now on.
Once the over-erasure takes place, the threshold voltage of the memory cell becomes negative, thereby hindering correct read or write of data.
To deal with the over-erasure, the conventional device carries out, after completing the drawing of the electrons from the floating gate 2, weak write by grounding the N-type source 3 and applying the voltage of 12 V to the control gate 1, thereby keeping the threshold voltage of the memory cell positive. Thus, the over-erasure can be remedied.
With the foregoing arrangement, the conventional over-erasure preventing device can remove the over-erasure state. However, once the memory cell has been broken owing to the over-erasure, this will present a problem of making data read and write impossible, even if the over-erasure state is remedied afterward.
In addition, since the weak write must be carried out after drawing out the electrons from the floating gate 2, a problem arises in that the erasing processing becomes complicated and time consuming.
Another technique is disclosed in Japanese patent application laid-open No. 7-272491/1995, in which the weak write is carried out while a leakage current due to the over-erasure is flowing. In this case also, as in the foregoing conventional example, once the memory cell has been broken owing to the over-erasure, a problem arises of making data read and write impossible, even if the over-erasure state is compensated.